SHAPES - Scalable software Hardware Architecture Platform for Embedded Systems (FP6-IST) (2006-01-01 - 2009-06-30) (»add to infobox)

Pier Stanislao PAOLUCCI, Ahmed JERRAYA, Lothar THIELE, Rainer LEUPERS, Piero VICINI, Werner GEURTS, Marcello COPPOLA, Luca FANUCCI, Luigi RAFFO, Georgios SAKAS, Marcus GRIMM, Joop GEIJSEN, Philippe KAJFASZ

ATMEL ROMA S.R.L. (ITC45 - Milano) (Italy), ASSOCIATION POUR LE DEVELOPPEMENT DES RECHERCHES AUPRES DES UNIVERSITES DE L'ACADEMIE DE GRENOBLE (ADR) (FR714 - Isère) (France), EIDGENOESSISCHE TECHNISCHE HOCHSCHULE ZUERICH (CH011 - Vaud) (Switzerland), RWTH AACHEN UNIVERSITY (DEA21 - Aachen, Kreisfreie Stadt) (Germany), THE NATIONAL INSTITUTE OF NUCLEAR PHYSICS (ITE43 - Roma) (Italy), TARGET COMPILER TECHNOLOGIES (BE242 - Arr. Leuven) (Belgium), STMICROELECTRONICS SA (FR105 - Hauts-de-Seine) (France), UNIVERSITA DI PISA (ITE17 - Pisa) (Italy), UNIVERSITA DEGLI STUDI DI CAGLIARI (ITG2 - Sardegna) (Italy), FRAUNHOFER GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V. (DE212 - München, Kreisfreie Stadt) (Germany), MEDCOM GESELLSCHAFT FUER MEDIZINISCHE BILDVERARBEITUNG MBH (DE711 - Darmstadt, Kreisfreie Stadt) (Germany), ESAOTE EUROPE B.V. (NL423 - Zuid-Limburg) (Netherlands), THALES COMMUNICATIONS S.A. (FR105 - Hauts-de-Seine) (France)

There is no processing power ceiling for low consumption, low cost, dense DSP for future embedded human-centric applications treating audio, video, ultrasound and antenna signals. Nanoscale systems on chip will integrate billion-gate designs. The challenge is to find a scalable HW/SW design style for future CMOS technologies. The main problem is wiring, which threats Moore's law. Tiled architectures suggest a possible HW path: 'small' processing tiles connected by 'short wires'. The SW challenge is to provide a simple and efficient programming environment. SHAPES investigates a groundbreaking HW/SW architecture paradigm. The heterogeneous SHAPES tile is composed of a VLIW floating-point DSP, a RISC, on chip memory, and a network interface. For optimal balance among parallelism, local memory, and IP reuse on future technologies the tile gate count is limited to a few million gates. The SHAPES routing fabric connects on-chip and off-chip tiles, weaving a distributed packet switching network. 3D next-neighbors engineering methodologies will be studied for off-chip networking and maximum system density. For efficient programming, SHAPES will investigate a layered system software which does not destroy algorithmic and distribution info provided by the programmer and which is fully aware of the HW paradigm. For efficiency and QoS, the system SW manages intra-tile and inter-tile latencies, bandwidths, computing resources, using static and dynamic profiling. The SW accesses the on-chip and off-chip networks through a homogeneous interface. The same HW and SW interface is adopted for integration with signal acquisition and reconfigurable logic tiles. Generation after generation, the number of tiles on a single-chip will grow, but the application will be portable. SHAPES will set a new density record with multi-Teraops single-board computers and multi-Petaops systems exploited by an efficient programming environment.

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