PICMOS - Photonic Interconnect Layer on CMOS by Wafer-Scale Integration (FP6-IST) (2004-01-01 - 2006-12-31) (»add to infobox)

Dries VAN THOURHOUT, Florence FUSALBA, Jean-Marc FEDELI, Chrystelle LAGAHE-BLANCHARD, Pierre VIKTOROVITCH, George HALKIAS, Meint SMIT, N. N., N. N.

INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW (BE242 - Arr. Leuven) (Belgium), STMICROELECTRONICS SA (FR105 - Hauts-de-Seine) (France), COMMISSARIAT A L'ENERGIE ATOMIQUE (CEA) (FR101 - Paris) (France), TRACIT TECHNOLOGIES (FR714 - Isère) (France), CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS) (FR101 - Paris) (France), NATIONAL CENTRE FOR SCIENTIFIC RESEARCH "DEMOKRITOS" (GR300 - Attiki) (Greece), TECHNICAL UNIVERSITY OF EINDHOVEN (NL414 - Zuidoost-Noord-Brabant) (Netherlands), ECOLE CENTRALE DE LYON (FR716 - Rhône) (France), INSTITUT NATIONAL DES SCIENCES APPLIQUEES DE LYON (FR716 - Rhône) (France)

For future generation electronic circuits a severe bottleneck is expected on the global interconnect level. One of the most promising solutions is the use of an optical interconnect layer. Therefore, PICMOS will demonstrate the feasibility of adding a photonic interconnect layer on top of silicon ICs. This interconnect layer will be fabricated by a combination of wafer bonding and wafer-scale processing steps. It will be planar and will be built from a high-density passive optical wiring circuit integrated with InP-based sources and detectors using a wafer bonding approach. Two different integration strategies will be investigated: a wafer-to-wafer bond technology where the photonic interconnect layer is fabricated in parallel with the electronic circuits wafer and where both wafers are subsequently bonded together and an above-IC approach where the interconnect layer is fabricated directly on top of the electronic circuits. For the first approach, SOI-waveguides allowing for very high-density wiring will be developed. For the above-IC approach, an innovative type of high-contrast polymer waveguides compatible with CMOS back-end processing will be developed. Both types of waveguides will be fabricated using standard CMOS-processing techniques. The III-V epi material for the active photonic devices will be bonded on top of the waveguide circuits and the substrate will be removed. The active devices will be defined in the remaining membrane. In all fabrication steps, only waferscale technologies will be employed with the only exception made for the bonding of the III-V semiconductor material. Because of the large size difference between silicon and InP wafers and the limited space occupied by the active photonic devices, a rapid die-to-wafer bonding step will be developed for this step. In parallel with the technological oriented work, system studies will define application domains for PICMOS and generic parameter specifications for all subcomponents.

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